1. Field of the Invention
The present invention relates generally to a semiconductor die assembly employing multiple semiconductor dice. More specifically, the present invention relates to a method and apparatus for increasing integrated circuit density by employing dual leads-over-chip (LOC) configured semiconductor dice in a symmetrically configured semiconductor die assembly.
2. State of the Art
High performance, low cost, increased miniaturization of components, and greater packaging density of integrated circuits have long been the goals of the computer industry. Greater integrated circuit density, for a given level of active component and internal conductor density, is conventionally limited by the space available within a packaging envelope and by the surface area, or xe2x80x9creal estatexe2x80x9d, available on a carrier substrate such as a printed circuit board.
For single, conventional lead frame mounted dies, this limitation is a result of the basic design. Conventional lead frame design inherently limits potential single-die package density because the die-attach paddle of the lead frame is usually as large or larger than the die residing on the paddle. The larger the die, the less space (relative to size of the die) that remains around the periphery of the die-attach paddle for bond pads for wire bonding. Furthermore, the inner lead finger ends on a lead frame may provide anchor points for the leads when the leads and the die are encapsulated, as with a filled polymer by transfer molding. These anchor points may be embodied as lateral flanges or bends or kinks in the lead finger. Therefore, as die size is increased in relation to package size, there is a corresponding reduction in the available depth along the sides of a package for encapsulant material to anchor to the lead fingers and provide a robust seal thereabout. Consequently, as the lead fingers are subjected to the normal stresses of trimming, forming and assembly with a carrier substrate such as a printed circuit board, the encapsulant material may crack and destroy the package seal, substantially increasing the probability of premature device failure.
One method of increasing integrated circuit density is to stack a plurality of dice vertically. U.S. Pat. No. 5,012,323, issued Apr. 30, 1991 to Farnworth teaches combining a pair of dice mounted on opposing sides of a lead frame. An upper die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. The lower die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wire bonds. The lower die is slightly larger than the upper die so that the lower die bond pads are accessible from above through an aperture in the lead frame such that wire bonds can be made from these bond pads to lead extensions. However, this arrangement has a major disadvantage from a production standpoint, since different size dice are required. Moreover, the lead frame design employed by Farnworth employs long wire bonds as well as extended lead runs between the die and the exterior of the package, and the lead frame configuration is rather complex.
U.S. Pat. No. 5,291,061, issued Mar. 1, 1994 to Ball teaches a multiple stacked die device that contains up to four dies which does not exceed the height of then-current single die packages. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wire bonding operation and thin-adhesive layers between the dies of the stack. However, Ball secures all of the dice to the same (upper) side of a lead frame, necessarily increasing bond wire length, even if some of the leads of the lead frame are bent upwardly.
U.S. Pat. No. 4,862,245, issued Aug. 29, 1989 to Pashby discloses a xe2x80x9cleads over chipxe2x80x9d (LOC) configured lead frame, wherein the inner lead finger ends of a dual-in-line package (DIP) configured lead frame extend over and are secured to the upper (active) surface of a semiconductor die through a dielectric layer. Wire bond length is thus shortened by placing the inner lead finger ends in close proximity to a central row of die bond pads. However, the Pashby LOC configuration as disclosed relates to mounting and bonding only a single die.
U.S. Pat. No. 5,804,874, issued Sep. 8, 1998 to An et al. discloses the stacking of two or more identical LOC configured semiconductor dice facing in the same direction. A lower die is adhered by its active surface to leads of a lower lead frame and wire bonded in LOC fashion, after which the active surface of at least one other die is adhered to leads of an upper lead frame in LOC fashion, then adhesively back bonded to the upper surface of the lower lead frame. The leads of the upper lead frame are electrically connected to those of the lower lead frame by thermocompression bonding. The An device, while providing increased circuit density, requires at least two, differently-configured LOC lead frames and wire bonding before the at least two dice are secured together. Moreover, the asymmetrical die arrangement and coverage of the wire bonds of the lower die by the upper die may induce an irregular flow front of filled polymer as the assembly is encapsulated by transfer molding resulting in incomplete encapsulation without voids and increased probability of wire bond sweep and consequent shorting.
Therefore, it would be advantageous to develop a technique and device for increasing integrated circuit density in the form of a semiconductor device assembly using substantially similar or identically sized, LOC configured dice back bonded in a symmetrical package configuration and employing a symmetrical, multi-piece lead frame configuration readily susceptible to transfer molded packaging.
The present invention relates to a method and apparatus for increasing the integrated circuit density of a semiconductor assembly, and in particular, a dual LOC semiconductor die assembly by stacking two LOC semiconductor dice back to back on opposing sides of a common base lead frame and extending lead fingers over the active surfaces of the dice for wire bonding to centrally located bond pads thereof.
In one embodiment, the present invention may include stacking a first die to a second die back to back with a base lead frame therebetween so that the active surfaces of the first and second dice are facing outward in substantially opposite directions. A first offset lead frame and second offset lead frame, each having a plurality of lead fingers, are attached to primary lead fingers of the base lead frame with the lead fingers of the offset lead frames configured to extend over the first and second die, respectively, in a cantilevered manner. The offset lead frame lead fingers may be electrically connected at inner ends thereof to bond pads of the die over which they extend, as by wire bonding, tape automated bonding or thermocompression bonding, while the outer ends of the lead fingers may be electrically connected to primary lead fingers of the base lead frame, as by spot welding, soldering or thermocompression bonding.
The semiconductor die assembly of the present invention may further include a dielectric packaging envelope which encapsulates the base lead frame with the primary lead fingers extending therebeyond, the first and second dice, the first and second lead offset frames and the lead finger connections to the bond pads and the primary lead fingers. The packaging may be effected by a transfer molding process which may be facilitated by the use of mutually superimposed dam bars of the first and second offset lead frames on opposing sides of dam bars of the base lead frame to prevent molten, filled polymer encapsulant from extruding out of the mold cavities placed over the first and second semiconductor dice between the primary lead fingers of the base lead frame. Following encapsulation, a trim and form operation is performed to remove excess portions of the offset lead frames as well as the dam bars and to separate the packages into individual dual LOC semiconductor die assemblies and appropriately configure outer ends of the primary lead fingers.
Accordingly, the LOC semiconductor assembly of the present invention increases integrated circuit density by providing a stacked first and second die in a back to back configuration with the base lead frame therebetween. By this opposing, stacked arrangement, the potential for electrical shorting between the first and second die is significantly reduced since the active surfaces of the first and second die are facing outwardly in opposite directions. Further, the first and second die are advantageously arranged with large back side surfaces in contact with the base lead frame so that heat generated by the dice during operation is effectively transferred to the base lead frame and then out of the package through the primary lead fingers. In addition, effective, void free transfer molding is facilitated by the symmetrical configuration. Finally and without limitation, initial attachment of both the first and second die in back to back relationship to a common lead frame in a symmetrical relationship facilitates manipulation of the assembly for attachment of the offset lead frames and wire bonding and reduces the potential for damage to the assembly.